In this case, we can use Toggle synchronizer as shown in the below diagram. If the control signal changes too fast then the multi-flop synchronizer cannot avoid the sampling of a metastable signal at the receiving clock domain. Do not place any combinational logic between synchronizer flip-flops to reduce the probability of metastability effect by reducing propagation delay between synchronizer flip-flops The glitch-free output should be driven from the transmitting clock domain to receiving clock domain, i.e., always the registered output from the transmitting clock domain should be driven to receiving clock domain and no combinational logic should be added between sending & receiving flipflops to avoid glitches. Protocol to be taken care of for Multi-Flop Synchronizer These multi-flop synchronizers can be used in the path of single-bit control signals. The most used synchronizer is the multi-flop synchronizer shown in the below diagramīy adding synchronizer Flip flop in the destination domain, it allows sufficient time for the oscillations to settle down and ensure that a stable output is obtained in the destination domain by preventing the sampling of metastable signal. In this paper, the most commonly used synchronizers are discussed. Different types of synchronization structures are available, and each structure has strict rules for implementation that should be verified. The synchronizer avoids sampling metastable signals at the destination. Larger MTBF indicates longer time periods between failures, while smaller MTBF indicates that metastability can happen frequently. Mean time before failure (MTBF) tells us how frequently the storage element can become metastable. Today’s SOC can have >10 4 CDC signals on a single chip. In a multi-clock design, metastability cannot be avoided but the detrimental effects of metastability can be neutralized by adding synchronizers. If the unstable data is fed to several other places in the design, it may also lead to a high current flow and even chip burnout in the worst case. Since the CDC signal can fluctuate for some period of time, the input logic in the receiving clock domain might recognize the logic level of the fluctuating signal to be different values and hence propagate erroneous signals into the receiving clock domain. When the signal is sampled in another clock domain and if there is any setup and hold time violation, the receiving register may become metastable and the output settles to some random value after an unknown amount of time. In a design with multiple clocks, clock domain crossing occurs whenever data is transferred from a flip-flop driven by one clock to a flip-flop driven by another clock.

Today’s device needs multiple clocks with increasing system integration, peripherals & external interfaces, and power management.

Different domain iclock